The present invention generally relates to a method of manufacturing a flash memory device, and more particularly, to a method of forming a resistor of a flash memory device, for forming a voltage divider resistor.
In fabricating a flash memory, a pump regulator employs a voltage divider resistor. The resistor must be insensitive to a temperature and a voltage. A gate or metal resistor has a low resistance value. Accordingly, a large area is required and drawing rules are complicated in order to construct a resistor of 10 KΩ or more. For this reason, only the polysilicon layer of the floating gate used in the flash memory device is used as the resistor in the conventional art. The polysilicon layer was appropriate for the resistor since it has less variation depending on a bias and temperature. In contrast, a junction resistor having a value of several hundreds of about ohm/sq. is formed as the junction and is great in variation depending on a bias and temperature. Accordingly, the junction resistor is not appropriate to use for the resistor.
FIGS. 1 and 2 are cross-sectional views illustrating a method of forming a polysilicon resistor of a NAND flash memory device by employing the conventional Shallow Trench Isolation (STI) process. FIGS. 1 and 2 illustrate a method of forming a resistor at a predetermined region of a peri region while forming a gate in which a floating gate and a control gate are laminated in a cell region.
Referring to FIG. 1, an isolation structure 12 of a Shallow Trench Isolation (STI) structure is formed on a semiconductor substrate 10. A first polysilicon layer 14 and a dielectric layer 16 are sequentially formed on the isolation structure 12.
A predetermined region of the dielectric layer 16 is etched and a second polysilicon layer 18 is formed on the entire structure. A predetermined region of the second polysilicon layer 18 is etched so that a predetermined region of the dielectric layer 16 is exposed, so that a portion in which the first polysilicon layer 14 and the second polysilicon layer 18 are connected is separated from a portion in which the second polysilicon layer 18 is formed on the dielectric layer 16.
An interlayer insulating film 20 is formed on the entire structure. A predetermined region of the interlayer insulating film 20 is etched to expose a predetermined region of the second polysilicon layer 18 connected to the first polysilicon layer 14, thereby forming a contact hole. A conductive layer is formed to fill the contact hole. The conductive layer is patterned to form a contact plug 22 and a line layer 24.
Referring to FIG. 2, an isolation structure 12 is formed on a semiconductor substrate 10. A first polysilicon layer 14, a dielectric layer 16, and a second polysilicon layer 18 are formed on the isolation structure 12. A part of the second polysilicon layer 18 formed on the dielectric layer 16 is etched so that the second polysilicon layer 18 remains only in a predetermined region on the dielectric layer 16.
An interlayer insulating film 20 is formed on the entire structure. The interlayer insulating film 20, the dielectric layer 16, and a predetermined region of the first polysilicon layer 14 are etched to form a contact hole. A conductive layer is formed to plug the contact hole. The conductive layer is patterned to form a contact plug 22 and a line layer 24.
However, if the contact plug 22 is directly connected to the first polysilicon layer 14 as shown in FIG. 2, it becomes difficult to secure process margin since the thickness of the first polysilicon layer is lowered due to the high integration level. Furthermore, as devices shrink, the margin of the photolithography process is shortened in constructing the polysilicon layer in view of the flash memory device. This makes exact patterning difficult.
A Self-Aligned Floating Gate (SAFG) structure has been proposed to resolve the above issue. If the SAFG structure is applied, however, the polysilicon layer is formed only on the active region, and is not formed on the field region.